The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of an interfacial barrier layer in devices with a high-K gate dielectric material layer.
Fabrication of a semiconductor device and an integrated circuit including the same begins with a semiconductor substrate and employs film formation, ion implantation, photolithographic, etching and deposition techniques to form various structural features in or on the semiconductor substrate to attain individual circuit components which are then interconnected to form ultimately an integrated circuit. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) circuits requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integrated circuits employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate dielectric material, usually referred to as a gate oxide, and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-type and n-type devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as reliability, circuit performance and cost advantages.
The drive towards increased miniaturization and the resultant limits of conventional gate oxide layers have served as an impetus for the development of newer, high dielectric constant (xe2x80x9chigh-Kxe2x80x9d) materials as substitutes for conventional silicon dioxide-based gate oxide layers. Since the drain current in a MOS device is inversely proportional to the gate oxide thickness, the gate oxide is typically made as thin as possible commensurate with the material""s breakdown potential and reliability.
Decreasing the thickness of the gate oxide layer between the gate electrode and the source/drain extension regions together with the relatively high electric field across the gate oxide layer, can undesirably cause charge carriers to tunnel across the gate oxide layer. This renders the transistor xe2x80x9cleakyxe2x80x9d, degrading its performance. To alleviate this problem, high-k dielectric materials are used as the gate insulator. Herein, a high-K gate oxide may be referred to as a high-K gate dielectric material layer, in order to emphasize that the gate dielectric comprises a high-K dielectric material rather than silicon dioxide.
One problem which has been encountered in integrating high-K dielectric materials into semiconductor devices, including devices such as EEPROMs and other flash memory devices, is the undesirable interaction between many high-K dielectric materials and the silicon used in other semiconductor device structures. Of particular concern herein is the interaction between the high-K dielectric material used for the high-K gate dielectric material and the silicon, polysilicon or polysilicon-germanium substrate upon which the high-K dielectric material is deposited. The undesirable interactions occur as a result of the high-K dielectric materials being deposited on these substrates.
One particular undesirable interaction which may occur is the oxidation of the silicon or polysilicon material in contact with a high-K gate dielectric material layer by oxygen used in forming the high-K dielectric material layer, and by the oxygen in the metal oxides of which most high-K dielectric materials are formed.
Hence, it would be highly advantageous to develop a process that would permit the use of optimum materials in the formation of a high-K gate dielectric material, without the problems which result from oxidation of silicon, polysilicon or polysilicon-germanium upon which the high-K dielectric material is deposited. Accordingly, there exists a need for a process of manufacturing semiconductor devices with a high-K dielectric material layer that improves device performance, while avoiding undesirable interactions between elements, such as the oxidation of silicon substrates or polysilicon gate electrodes by the high-K gate dielectric materials deposited thereon. In particular, a need remains for a process of forming a high-K dielectric material over a silicon, polysilicon or polysilicon-germanium substrate while avoiding or reversing the effects of oxidation of the substrate at the interface between the silicon, polysilicon or polysilicon-germanium substrate and the high-K dielectric material.
In one embodiment, the present invention relates to a process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, comprising depositing on the silicon substrate a layer comprising at least one high-K dielectric material, whereby a quantity of silicon dioxide is formed at an interface between the silicon substrate and the high-K dielectric material layer; depositing on the high-K dielectric material layer a layer of a metal; and diffusing the metal through the high-K dielectric material layer, whereby the metal reduces at least a portion of the silicon dioxide to silicon and the metal is oxidized to form a dielectric material having a K value greater than silicon dioxide.
In another embodiment, the present invention relates to a process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, including steps of depositing on the silicon substrate a layer comprising at least one high-K dielectric material, whereby a quantity of silicon dioxide is formed at an interface between the silicon substrate and the high-K dielectric material layer; implanting a metal to a vicinity of the silicon dioxide; and subjecting the metal to conditions whereby the metal reduces at least a portion of the silicon dioxide to silicon and the metal is oxidized to form a dielectric material having a K value greater than silicon dioxide.
In another embodiment, the present invention relates to a semiconductor device, including a silicon substrate; on the silicon substrate a layer of a high-K dielectric material; a quantity of silicon dioxide at an interface between the silicon substrate and the high-K dielectric material layer; and a layer of metal deposited on the high-K dielectric material layer, in which the metal is capable of reacting with at least a portion of the silicon dioxide to form a metal oxide having a K value greater than silicon dioxide.
In another embodiment, the present invention relates to a semiconductor device, including a silicon substrate; on the silicon substrate a layer of a high-K dielectric material; a quantity of silicon dioxide at an interface between the silicon substrate and the high-K dielectric material layer; and a metal implanted or diffused through the high-K dielectric material layer to the interface, in which the metal is capable of reacting with at least a portion of the silicon dioxide to form a metal oxide having a K value greater than silicon dioxide.
In one embodiment, the metal preferentially forms an oxide or a silicate rather than a silicide. In one embodiment, the Gibbs free energy of the metal oxide is more negative than the Gibbs free energy of silicon dioxide. In one embodiment, the Gibbs free energy of the metal oxide is more negative than the Gibbs free energy of the metal silicide.
Thus, the present invention provides a solution to the problem of forming a high-K dielectric material layer on a silicon substrate or of forming a polysilicon or polysilicon-germanium gate electrode on a high-K dielectric material layer, while avoiding or reversing resulting oxidation of the silicon or polysilicon.